The spread of satellite broadcasts and microwave communications has been accompanied by increasing demand for low-noise amplification elements used in the first stage of the high-frequency amplifying circuit that receives the signal. In particular, field-effect transistors (FETs) formed on a gallium-arsenide (GaAs) substrate are primarily used for satellite broadcasts having a frequency on the order of 10 GHz.
In such a semiconductor element, what is sought is that the semiconductor element itself does not produce noise anew to the greatest degree possible when an extremely weak high-frequency signal as from an antenna is amplified by an initial input stage. That is, what is sought is a semiconductor element having a small noise figure (NF). The term “noise figure” relates to the magnification from a power ratio of a signal component to a noise component at an input terminal to a power ratio of the signal component to the noise component at an output terminal, i.e., the rate of increase in the noise component, and it indicates noise added on by the semiconductor elements in the amplifier circuit. A minimum noise figure NFmin, which is the minimum noise figure obtained by adjusting input/output impedances under certain bias conditions, and associated gain (Ga), which is the power gain at such time, are used as indices for evaluating semiconductor elements. Both of these values are expressed in dB units of a common logarithm.
In the case of a FET serving as the semiconductor element in an amplifying circuit, the minimum noise figure NFmin should be made small. To achieve this, mutual conductance gm should be enlarged and gate capacitance Cgs, gate-series resistance Rg and source-series resistance Rs, which are parasitic components, should be made small. The resistance component in particular is a source of thermal noise. Further, with regard to power gain or associated gain Ga as the amplification factor, it is desired that cut-off frequency ft be raised and that drain conductance gd indicative of saturation of drain current be made small. Enlarging mutual conductance gm is effective in order to raise the cut-off frequency ft, and reducing gate length Lg is effective in order to reduce gate capacitance Cgs. In order to enlarge mutual conductance gm, it is desired that gate length Lg be reduced and that carrier mobility of the channel semiconductor layer be raised.
Patent Document 1 discloses a high electron mobility transistor (HEMT) representing early technology regarding low-noise FETs. The semiconductor device described in Patent Document 1 includes a semiconductor substrate on which are provided a single semiconductor channel layer of high resistance and an impurity-doped semiconductor layer having an electron affinity lower than that of the single semiconductor channel layer, these forming a heterojunction; a gate electrode provided on this semiconductor layer; and a source electrode and a drain electrode formed on respective ones of the sides of the gate electrode. Patent Document 1 indicates that in such a semiconductor device, a two-dimensional electron gas (2DEG) exhibiting a high electron mobility is induced within an i-type GaAs layer in the vicinity of the heterojunction interface, e.g., in the vicinity of the interface between an n-type AlGaAs layer and the undoped (i-type) GaAs layer. Application to low-noise FETs began with this semiconductor device and semiconductor elements with a large mutual conductance gm and small noise figure NF have been realized.
FIG. 25 is a sectional view of a field-effect transistor 501 described in Non-Patent Document 1. The field-effect transistor 501 described in Non-Patent Document 1 has a semi-insulating GaAs substrate 502 on which are provided an undoped (i-type) GaAs layer 503 serving as a buffer layer; an undoped (i-type) InGaAs layer 504 serving as a channel layer; an undoped (i-type) AlGaAs layer 505 serving as a spacer layer; an n-type AlGaAs layer 506 serving as an electron supply layer; and an n-type GaAs layer 507 serving as a contact layer. This field-effect transistor is also referred to as a “pseudomorphic HEMT”. At a heterojunction interface having distortion between the n-type AlGaAs layer 506 and the i-type InGaAs layer 504, a higher electron mobility is obtained in comparison with an i-type GaAs layer. With a low-noise FET to which this higher electron mobility has been applied, the minimum noise figure NFmin declines and the associated gain Ga rises, meaning that performance is enhanced. In FIG. 25, a gate electrode 510 exhibiting Schottky contact is provided so as to contact the surface of a recess formed part of the way into the n-type AlGaAs electron supply layer 506. An ohmic-contact pair of source electrode 508 and drain electrode 509 is provided on respective remaining portions of the n-type GaAs contact layer 507 on both flanks of the gate electrode 510.
A method of manufacturing the field-effect transistor set forth in FIG. 25 will be described. First, the undoped (i-type) GaAs buffer layer 503, undoped (i-type) InGaAs channel layer 504, undoped (i-type) AlGaAs spacer layer 505, n-type AlGaAs electron supply layer 506 and n-type GaAs contact layer 507 are grown successively on the GaAs substrate 502 by molecular beam epitaxy (MBE) or metal organic vapor-phase epitaxy (MOVPE).
First, as a method of manufacturing an FET, the electrically conductive semiconductor layers, namely the n-type AlGaAs electron supply layer 506 and n-type GaAs contact layer 507 grown epitaxially on the GaAs substrate, are isolated by mesa etching. Next, a pair of mutually opposing ohmic electrodes is formed on the remaining regions of the electrically conductive semiconductor layers. Further, monitor elements having ohmic-electrode lead-pad terminals are provided on portions of the substrate in such a manner that current can be measured by bringing a metal needle into abutting contact with the pair of ohmic electrodes. Next, a photoresist film having a slender opening is formed between the pair of ohmic electrodes so as to cross the remaining regions of the conductive semiconductor layers. Further, an opening through which the metal needle makes contact is formed above the pad terminals of the ohmic electrodes. Next, a recess is formed part of the way into the n-type AlGaAs electron supply layer 506 using an etching solution. Such etching is repeated until the current that flows between the pad terminals of the monitor elements falls within a prescribed range of current values. Next, if the prescribed current value is attained, a Schottky metal such as aluminum (Al) is vapor-deposited in the openings, a lift-off treatment is applied by dissolving the photoresist mask using an organic solvent, and the gate electrode 510 is formed in the recess. Further, the ohmic electrodes that have been formed on the n-type GaAs contact layer 507 on both sides of the gate electrode become the source electrode 508 and drain electrode 509. The basic FET structure is thus formed.
Primarily, a dilute solution of sulfuric acid or phosphoric acid, hydrogen peroxide solution and pure water is used as the etching solution for the recess. With this etching solution, GaAs and AlGaAs can be etched isotropically at the same etching speed. On the other hand, if dry etching is used to form the recess, the semiconductor layer is damaged. In order to manufacture a low-noise FET, therefore, wet etching is better.
With wet etching, however, making the AlGaAs layer an etching-stop layer was difficult. Accordingly, in a field-effect transistor described in Patent Document 2, wet etching is controlled by using an InGaP layer as a stop layer.
FIG. 26 is a sectional view illustrating the field-effect transistor 511 described in Patent Document 2. The field-effect transistor (FET) 511 described in Patent Document 2 will be described based upon the method of manufacture. An epitaxial substrate used in the FET 511 is built up on a semi-insulating GaAs substrate 512 using metal organic vapor-phase epitaxy (MOVPE), by way of example. A buffer layer 513 of undoped (i-type) GaAs or undoped (i-type) AlGaAs, an n-type AlGaAs electron supply layer (lower layer) 514, an undoped (i-type) InGaAs channel layer 515, an n-type AlGaAs electron supply layer (upper layer) 516, an undoped (i-type) AlGaAs Schottky layer 517, an n-type InGaP contact lower layer 518 and an n-type GaAs contact upper layer 519 are grown epitaxially on the semi-insulating GaAs substrate 512 in the order mentioned.
Next, by using an etching solution of sulfuric acid and hydrogen peroxide solution (H2SO4—H2O2—H2O), a first recess opening penetrating the n-type GaAs contact upper layer 519 is formed. Since almost no etching of the n-type InGaP contact lower layer 518 by this etching solution takes place, etching in the depth direction of the first recess opening is stopped automatically at the moment the n-type GaAs contact upper layer 519 is penetrated and the surface of the n-type InGaP contact lower layer 518 is exposed. Next, after a photoresist film is formed, a second recess opening having a width smaller than that of the first recess opening is formed within the first recess opening using, e.g., a dilute hydrochloric acid (HCl—H2O) etching solution. Since almost no etching of the GaAs or AlGaAs layer takes place by this solution, etching in the depth direction of the second recess opening is stopped automatically at the moment the n-type InGaP contact lower layer 518 is penetrated and the surface of the undoped AlGaAs Schottky layer 517 is exposed. Next, a gate electrode 522 is formed on the surface of the undoped AlGaAs Schottky layer 517 exposed at the bottom of the second recess opening. Finally, a source electrode 520 and a drain electrode 521 are formed on the surface of the n-type GaAs contact upper layer 519 on respective ones of the two sides bracketing the gate electrode 522 and first recess opening. Ohmic contact is then formed by a thermal treatment.
FIG. 27 is a sectional view illustrating a field-effect transistor 531 described in Patent Document 3. An n-type InGaP contact layer 534 is utilized as a wet-etching stop layer also in the field-effect transistor 531 described in Patent Document 3. However, one difference from Patent Document 2 is that the lower portion of a gate electrode 538 is embedded with its bottom surface in contact with an n-type AlGaAs electron supply layer 533 and its side surface in contact with the n-type InGaP contact layer 534. In addition, a channel layer 532 of undoped (i-type) GaAs or InGaAs is provided beneath the n-type AlGaAs electron supply layer 533, an n-type GaAs contact layer 535 is provided on the n-type InGaP contact layer 534, and a source electrode 536 and a drain electrode 537 are provided on respective sides of the contact layer 535.
Patent Documents 4 and 5 disclose a wiring structure of a field-effect transistor (semiconductor device) of improved noise characteristic and gain characteristic. By placing drain wiring over source wiring with a gap interposed therebetween (an air-bridge scheme), parasitic capacitance between the intersecting wiring traces is reduced.
Patent Document 6 discloses a method of manufacturing a semiconductor device having shallow ohmic contact, wherein the method builds up an AuGe film and Au film on a thin nickel (Ni) film and applies an alloying thermal treatment.
Patent Document 7 discloses a heterojunction field-effect transistor in which electron mobility of a two-dimensional electron gas is raised by thinly inserting an i-type GaAs layer as a spacer layer, the thickness of which is on the order of 2 nm, at the interface of an n-type AlGaAs layer and i-type InGaAs layer.
Patent Document 8 discloses a molded package having a hollow structure, and Patent Document 9 a molded cap for a semiconductor device.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-A-56-94780
[Patent Document 2]
Japanese Patent Kokai Publication No. JP-A-7-335867 (FIG. 1) (Related document: Japanese Patent No. 2581452)
[Patent Document 3]
Japanese Patent Kokai Publication No. JP-A-8-340012 (FIG. 1) (Related document: Japanese Patent No. 2685032)
[Patent Document 4]
Japanese Patent Kokai Publication No. JP-A-4-96339 (Related document: Japanese Patent No. 2626209)
[Patent Document 5]
Japanese Patent Kokai Publication No. JP-A-5-211179 (Related document: Japanese Patent No. 2822739)
[Patent Document 6]
Japanese Patent Kokai Publication No. JP-A-3-231424 (Related document: Japanese Patent No. 2611474)
[Patent Document 7]
Japanese Patent Kokai Publication No. JP-A-6-163599 (Related document: Japanese Patent No. 2755076)
[Patent Document 8]
Japanese Patent Kokai Publication No. JP-P2002-334944A
[Patent Document 9]
Japanese Patent Kokai Publication No. JP-A-9-213827 (Related document: Japanese Patent No. 2755244)
[Non-Patent Document 1]
H. Tokuda: “Low-noise HEMT—Deciding the Characteristics Thereof” [pp. 239-260, FIG. 9.6(b) on page 243)]; (Collected Papers) Semiconductor Research Vol. 35; Crystal Growth of Compound Semiconductor and Evaluation; Editor: Junichi Nishizawa; Publisher: Kogyo Chosakai K. K.; Publication Date: Aug. 5, 1991; ISBN 4-7693-1089-7 C3055